// ******************************************************************************
// Copyright     :  Copyright (C) 2021, Hisilicon Technologies Co. Ltd.
// File name     :  hipciec_nvme_global_reg_reg_offset.h
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2021/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2
// History       :  xxx 2021/10/24 11:22:07 Create file
// ******************************************************************************

#ifndef __HIPCIEC_NVME_GLOBAL_REG_REG_OFFSET_H__
#define __HIPCIEC_NVME_GLOBAL_REG_REG_OFFSET_H__

/* HIPCIEC_NVME_GLOBAL_REG Base address of Module's Register */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE                       (0x102000)

/******************************************************************************/
/*                      HiPCIECTRL40V200 HIPCIEC_NVME_GLOBAL_REG Registers' Definitions                            */
/******************************************************************************/

#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF_WR_CTRL_REG_INT_STS_0_REG    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x40)    /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF_WR_CTRL_REG_INT_STS_1_REG    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x140)   /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_0_REG    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x240)   /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_1_REG    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x340)   /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_2_REG    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x440)   /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_3_REG    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x540)   /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_4_REG    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x640)   /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_5_REG    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x740)   /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_6_REG    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x840)   /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_7_REG    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x940)   /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_8_REG    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA40)   /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_9_REG    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB40)   /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_10_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xC40)   /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_11_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xD40)   /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_12_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xE40)   /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_13_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xF40)   /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_14_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x1040)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_15_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x1140)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_16_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x1240)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_17_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x1340)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_18_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x1440)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_19_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x1540)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_20_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x1640)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_21_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x1740)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_22_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x1840)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_23_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x1940)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_24_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x1A40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_25_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x1B40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_26_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x1C40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_27_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x1D40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_28_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x1E40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_29_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x1F40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_30_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x2040)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_31_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x2140)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_32_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x2240)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_33_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x2340)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_34_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x2440)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_35_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x2540)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_36_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x2640)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_37_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x2740)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_38_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x2840)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_39_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x2940)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_40_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x2A40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_41_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x2B40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_42_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x2C40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_43_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x2D40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_44_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x2E40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_45_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x2F40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_46_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x3040)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_47_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x3140)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_48_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x3240)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_49_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x3340)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_50_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x3440)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_51_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x3540)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_52_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x3640)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_53_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x3740)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_54_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x3840)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_55_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x3940)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_56_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x3A40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_57_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x3B40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_58_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x3C40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_59_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x3D40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_60_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x3E40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_61_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x3F40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_62_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x4040)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_63_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x4140)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_64_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x4240)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_65_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x4340)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_66_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x4440)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_67_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x4540)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_68_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x4640)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_69_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x4740)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_70_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x4840)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_71_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x4940)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_72_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x4A40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_73_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x4B40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_74_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x4C40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_75_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x4D40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_76_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x4E40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_77_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x4F40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_78_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x5040)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_79_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x5140)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_80_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x5240)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_81_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x5340)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_82_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x5440)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_83_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x5540)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_84_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x5640)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_85_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x5740)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_86_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x5840)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_87_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x5940)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_88_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x5A40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_89_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x5B40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_90_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x5C40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_91_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x5D40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_92_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x5E40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_93_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x5F40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_94_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x6040)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_95_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x6140)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_96_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x6240)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_97_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x6340)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_98_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x6440)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_99_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x6540)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_100_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x6640)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_101_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x6740)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_102_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x6840)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_103_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x6940)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_104_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x6A40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_105_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x6B40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_106_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x6C40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_107_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x6D40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_108_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x6E40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_109_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x6F40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_110_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x7040)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_111_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x7140)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_112_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x7240)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_113_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x7340)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_114_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x7440)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_115_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x7540)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_116_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x7640)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_117_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x7740)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_118_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x7840)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_119_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x7940)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_120_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x7A40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_121_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x7B40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_122_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x7C40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_123_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x7D40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_124_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x7E40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_125_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x7F40)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_WR_CTRL_REG_INT_STS_126_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x8040)  /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_CTRL_MISC_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA000)  /* NVMe Local Misc Control */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SRIOV_MODE_CTRL_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA004)  /* NVMe SRIOV Mode Control */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF2_BAR0_DB_ATU_LOW_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA008)  /* PF2 BAR0 doorbell ATU Register Low */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF2_BAR0_DB_ATU_HIGH_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA00C)  /* PF2 BAR0 doorbell ATU Register High */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF2_VF_BAR0_DB_ATU_LOW_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA010)  /* PF2 VF BAR0 doorbell ATU Register Low */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF2_VF_BAR0_DB_ATU_HIGH_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA014)  /* PF2 VF BAR0 doorbell ATU Register High */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF3_BAR0_DB_ATU_LOW_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA018)  /* PF3 BAR0 doorbell ATU Register Low */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF3_BAR0_DB_ATU_HIGH_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA01C)  /* PF3 BAR0 doorbell ATU Register High */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF3_VF_BAR0_DB_ATU_LOW_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA020)  /* PF3 VF BAR0 doorbell ATU Register Low */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF3_VF_BAR0_DB_ATU_HIGH_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA024)  /* PF3 VF BAR0 doorbell ATU Register High */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_INT_COAL_TIME_CNT_UNIT_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA028)  /* Interrupt Coal Timer Count Unit */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_INT_COAL_MASK0_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA02C)  /* int coal mask0 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_INT_COAL_MASK1_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA030)  /* int coal mask1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_INT_COAL_MASK2_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA034)  /* int coal mask2 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_INT_COAL_MASK3_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA038)  /* int coal mask3 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_INT_COAL_MASK4_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA03C)  /* int coal mask4 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_INT_COAL_MASK5_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA040)  /* int coal mask5 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_INT_COAL_MASK6_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA044)  /* int coal mask6 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_INT_COAL_MASK7_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA048)  /* int coal mask7 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_INT_COAL_MASK8_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA04C)  /* int coal mask8 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_INT_COAL_MASK9_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA050)  /* int coal mask9 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_INT_COAL_MASK10_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA054)  /* int coal mask10 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_INT_COAL_MASK11_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA058)  /* int coal mask11 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_INT_COAL_MASK12_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA05C)  /* int coal mask12 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_INT_COAL_MASK13_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA060)  /* int coal mask13 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_INT_COAL_MASK14_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA064)  /* int coal mask14 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_INT_COAL_MASK15_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA068)  /* int coal mask15 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_MASK0_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA06C)  /* cqdb_int mask0 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_MASK1_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA070)  /* cqdb_int mask1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_MASK2_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA074)  /* cqdb_int mask2 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_MASK3_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA078)  /* cqdb_int mask3 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_MASK4_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA07C)  /* cqdb_int mask4 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_MASK5_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA080)  /* cqdb_int mask5 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_MASK6_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA084)  /* cqdb_int mask6 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_MASK7_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA088)  /* cqdb_int mask7 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_MASK8_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA08C)  /* cqdb_int mask8 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_MASK9_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA090)  /* cqdb_int mask9 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_MASK10_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA094)  /* cqdb_int mask10 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_MASK11_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA098)  /* cqdb_int mask11 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_MASK12_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA09C)  /* cqdb_int mask12 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_MASK13_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0A0)  /* cqdb_int mask13 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_MASK14_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0A4)  /* cqdb_int mask14 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_MASK15_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0A8)  /* cqdb_int mask15 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_MASK0_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0AC)  /* wrptr_int mask0 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_MASK1_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0B0)  /* wrptr_int mask1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_MASK2_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0B4)  /* wrptr_int mask2 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_MASK3_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0B8)  /* wrptr_int mask3 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_MASK4_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0BC)  /* wrptr_int mask4 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_MASK5_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0C0)  /* wrptr_int mask5 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_MASK6_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0C4)  /* wrptr_int mask6 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_MASK7_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0C8)  /* wrptr_int mask7 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_DB_INT_COAL_CFG_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0CC)  /* Doorbell Interrupt Coal Cfg */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_ENG_WORK_MODE_SEL_REG           (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0D0)  /* select cs version or es version */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_MASK8_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0D4)  /* wrptr_int mask8 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_MASK9_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0D8)  /* wrptr_int mask9 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_MASK10_REG            (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0DC)  /* wrptr_int mask10 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_MASK11_REG            (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0E0)  /* wrptr_int mask11 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_MASK12_REG            (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0E4)  /* wrptr_int mask12 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_MASK13_REG            (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0E8)  /* wrptr_int mask13 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_MASK14_REG            (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0EC)  /* wrptr_int mask14 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_MASK15_REG            (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0F0)  /* wrptr_int mask15 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_STS0_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0F4)  /* sqdb_int sts0 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_STS1_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0F8)  /* sqdb_int sts1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_STS2_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA0FC)  /* sqdb_int sts2 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_STS3_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA100)  /* sqdb_int sts3 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_STS4_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA104)  /* sqdb_int sts4 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_STS5_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA108)  /* sqdb_int sts5 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_STS6_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA10C)  /* sqdb_int sts6 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_STS7_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA110)  /* sqdb_int sts7 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_STS8_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA114)  /* sqdb_int sts8 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_STS9_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA118)  /* sqdb_int sts9 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_STS10_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA11C)  /* sqdb_int sts10 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_STS11_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA120)  /* sqdb_int sts11 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_STS12_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA124)  /* sqdb_int sts12 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_STS13_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA128)  /* sqdb_int sts13 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_STS14_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA12C)  /* sqdb_int sts14 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_STS15_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA130)  /* sqdb_int sts15 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_STS0_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA134)  /* cqdb_int sts0 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_STS1_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA138)  /* cqdb_int sts1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_STS2_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA13C)  /* cqdb_int sts2 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_STS3_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA140)  /* cqdb_int sts3 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_STS4_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA144)  /* cqdb_int sts4 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_STS5_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA148)  /* cqdb_int sts5 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_STS6_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA14C)  /* cqdb_int sts6 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_STS7_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA150)  /* cqdb_int sts7 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_STS8_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA154)  /* cqdb_int sts8 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_STS9_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA158)  /* cqdb_int sts9 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_STS10_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA15C)  /* cqdb_int sts10 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_STS11_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA160)  /* cqdb_int sts11 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_STS12_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA164)  /* cqdb_int sts12 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_STS13_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA168)  /* cqdb_int sts13 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_STS14_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA16C)  /* cqdb_int sts14 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_STS15_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA170)  /* cqdb_int sts15 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_STS0_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA174)  /* wrptr_int sts0 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_STS1_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA178)  /* wrptr_int sts1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_STS2_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA17C)  /* wrptr_int sts2 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_STS3_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA180)  /* wrptr_int sts3 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_STS4_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA184)  /* wrptr_int sts4 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_STS5_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA188)  /* wrptr_int sts5 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_STS6_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA18C)  /* wrptr_int sts6 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_STS7_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA190)  /* wrptr_int sts7 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_STS8_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA194)  /* wrptr_int sts8 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_STS9_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA198)  /* wrptr_int sts9 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_STS10_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA19C)  /* wrptr_int sts10 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_STS11_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA1A0)  /* wrptr_int sts11 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_STS12_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA1A4)  /* wrptr_int sts12 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_STS13_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA1A8)  /* wrptr_int sts13 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_STS14_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA1AC)  /* wrptr_int sts14 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_INT_STS15_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA1B0)  /* wrptr_int sts15 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_MASK0_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA1F4)  /* sqdb_int mask0 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_MASK1_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA1F8)  /* sqdb_int mask1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_MASK2_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA1FC)  /* sqdb_int mask2 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_MASK3_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA200)  /* sqdb_int mask3 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_MASK4_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA204)  /* sqdb_int mask4 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_MASK5_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA208)  /* sqdb_int mask5 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_MASK6_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA20C)  /* sqdb_int mask6 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_MASK7_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA210)  /* sqdb_int mask7 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_MASK8_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA214)  /* sqdb_int mask8 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_MASK9_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA218)  /* sqdb_int mask9 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_MASK10_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA21C)  /* sqdb_int mask10 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_MASK11_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA220)  /* sqdb_int mask11 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_MASK12_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA224)  /* sqdb_int mask12 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_MASK13_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA228)  /* sqdb_int mask13 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_MASK14_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA22C)  /* sqdb_int mask14 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_MASK15_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA230)  /* sqdb_int mask15 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_CFG0_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA234)  /* sqdb_int cfg0 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_CFG1_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA238)  /* sqdb_int cfg1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_CFG2_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA23C)  /* sqdb_int cfg2 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_CFG3_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA240)  /* sqdb_int cfg3 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_CFG4_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA244)  /* sqdb_int cfg4 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_CFG5_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA248)  /* sqdb_int cfg5 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_CFG6_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA24C)  /* sqdb_int cfg6 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_CFG7_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA250)  /* sqdb_int cfg7 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_CFG8_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA254)  /* sqdb_int cfg8 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_CFG9_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA258)  /* sqdb_int cfg9 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_CFG10_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA25C)  /* sqdb_int cfg10 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_CFG11_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA260)  /* sqdb_int cfg11 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_CFG12_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA264)  /* sqdb_int cfg12 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_CFG13_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA268)  /* sqdb_int cfg13 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_CFG14_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA26C)  /* sqdb_int cfg14 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQDB_INT_CFG15_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA270)  /* sqdb_int cfg15 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_CFG0_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA274)  /* cqdb_int cfg0 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_CFG1_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA278)  /* cqdb_int cfg1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_CFG2_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA27C)  /* cqdb_int cfg2 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_CFG3_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA280)  /* cqdb_int cfg3 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_CFG4_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA284)  /* cqdb_int cfg4 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_CFG5_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA288)  /* cqdb_int cfg5 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_CFG6_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA28C)  /* cqdb_int cfg6 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_CFG7_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA290)  /* cqdb_int cfg7 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_CFG8_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA294)  /* cqdb_int cfg8 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_CFG9_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA298)  /* cqdb_int cfg9 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_CFG10_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA29C)  /* cqdb_int cfg10 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_CFG11_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2A0)  /* cqdb_int cfg11 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_CFG12_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2A4)  /* cqdb_int cfg12 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_CFG13_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2A8)  /* cqdb_int cfg13 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_CFG14_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2AC)  /* cqdb_int cfg14 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQDB_INT_CFG15_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2B0)  /* cqdb_int cfg15 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_DB_INT_CFG0_REG           (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2B4)  /* wrptr_db_int cfg0 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_DB_INT_CFG1_REG           (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2B8)  /* wrptr_db_int cfg1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_DB_INT_CFG2_REG           (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2BC)  /* wrptr_db_int cfg2 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_DB_INT_CFG3_REG           (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2C0)  /* wrptr_db_int cfg3 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_DB_INT_CFG4_REG           (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2C4)  /* wrptr_db_int cfg4 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_DB_INT_CFG5_REG           (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2C8)  /* wrptr_db_int cfg5 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_DB_INT_CFG6_REG           (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2CC)  /* wrptr_db_int cfg6 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_DB_INT_CFG7_REG           (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2D0)  /* wrptr_db_int cfg7 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_DB_INT_CFG8_REG           (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2D4)  /* wrptr_db_int cfg8 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_DB_INT_CFG9_REG           (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2D8)  /* wrptr_db_int cfg9 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_DB_INT_CFG10_REG          (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2DC)  /* wrptr_db_int cfg10 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_DB_INT_CFG11_REG          (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2E0)  /* wrptr_db_int cfg11 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_DB_INT_CFG12_REG          (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2E4)  /* wrptr_db_int cfg12 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_DB_INT_CFG13_REG          (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2E8)  /* wrptr_db_int cfg13 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_DB_INT_CFG14_REG          (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2EC)  /* wrptr_db_int cfg14 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WRPTR_DB_INT_CFG15_REG          (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2F0)  /* wrptr_db_int cfg15 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_INT_MOD_SEL_REG            (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2F4)  /* nvme int mode select */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_INT_LEVEL_SEL_REG          (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2F8)  /* nvme int_levlel_cfg */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_QUEUE_DEL_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA2FC)  /* nvme_queue_del */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQ_ERR_STS0_REG                 (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA300)  /* nvme_sqdb_err_sts */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQ_ERR_STS1_REG                 (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA304)  /* nvme_sqdb_err_sts1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_RO_CFG_REG                      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA308)  /* nvme_sq_order_cfg */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_QUEUE_EN0_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA30C)  /* queue_enable0 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_QUEUE_EN1_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA310)  /* queue_enable1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_QUEUE_EN2_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA314)  /* queue_enable2 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_QUEUE_EN3_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA318)  /* queue_enable3 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_QUEUE_EN4_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA31C)  /* queue_enable4 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_QUEUE_EN5_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA320)  /* queue_enable5 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_QUEUE_EN6_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA324)  /* queue_enable6 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_QUEUE_EN7_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA328)  /* queue_enable7 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_QUEUE_EN8_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA32C)  /* queue_enable8 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_QUEUE_EN9_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA330)  /* queue_enable9 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_QUEUE_EN10_REG                  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA334)  /* queue_enable10 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_QUEUE_EN11_REG                  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA338)  /* queue_enable11 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_QUEUE_EN12_REG                  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA33C)  /* queue_enable12 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_QUEUE_EN13_REG                  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA340)  /* queue_enable13 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_QUEUE_EN14_REG                  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA344)  /* queue_enable14 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_QUEUE_EN15_REG                  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA348)  /* queue_enable15 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT0_REG                 (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA34C)  /* cq_err_int0 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT1_REG                 (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA350)  /* cq_err_int1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT2_REG                 (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA354)  /* cq_err_int2 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT3_REG                 (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA358)  /* cq_err_int3 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT4_REG                 (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA35C)  /* cq_err_int4 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT5_REG                 (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA360)  /* cq_err_int5 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT6_REG                 (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA364)  /* cq_err_int6 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT7_REG                 (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA368)  /* cq_err_int7 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT8_REG                 (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA36C)  /* cq_err_int8 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT9_REG                 (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA370)  /* cq_err_int9 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT10_REG                (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA374)  /* cq_err_int10 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT11_REG                (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA378)  /* cq_err_int11 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT12_REG                (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA37C)  /* cq_err_int12 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT13_REG                (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA380)  /* cq_err_int13 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT14_REG                (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA384)  /* cq_err_int14 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT15_REG                (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA388)  /* cq_err_int15 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT_CFG0_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA38C)  /* cq_err_int_cfg0 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT_CFG1_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA390)  /* cq_err_int_cfg1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT_CFG2_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA394)  /* cq_err_int_cfg2 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT_CFG3_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA398)  /* cq_err_int_cfg3 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT_CFG4_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA39C)  /* cq_err_int_cfg4 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT_CFG5_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA3A0)  /* cq_err_int_cfg5 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT_CFG6_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA3A4)  /* cq_err_int_cfg6 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT_CFG7_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA3A8)  /* cq_err_int_cfg7 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT_CFG8_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA3AC)  /* cq_err_int_cfg8 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT_CFG9_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA3B0)  /* cq_err_int_cfg9 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT_CFG10_REG            (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA3B4)  /* cq_err_int_cfg10 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT_CFG11_REG            (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA3B8)  /* cq_err_int_cfg11 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT_CFG12_REG            (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA3BC)  /* cq_err_int_cfg12 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT_CFG13_REG            (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA3C0)  /* cq_err_int_cfg13 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT_CFG14_REG            (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA3C4)  /* cq_err_int_cfg14 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_CQ_ERR_INT_CFG15_REG            (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA3C8)  /* cq_err_int_cfg15 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WR_PTR_BASE_ADDDR_LOW_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA400)  /* low 32 bit of nvmer wr_ptr base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_WR_PTR_BASE_ADDDR_HIGH_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA404)  /* high 32 bit of nvmer wr_ptr base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_MEMORY_BASE_ADDDR_LOW_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA408)  /* low 32 bit of nvmer memory base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_MEMORY_BASE_ADDDR_HIGH_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA40C)  /* high 32 bit of nvmer memory base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_MEMORY_SPACE_LOW_REG            (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA410)  /* low 32 bit of nvmer memoryspace for a SQ */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_MEMORY_SPACE_HIGH_REG           (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA414)  /* high 32 bit of nvmer memoryspace for a SQ */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_DB_STRD_REG                     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA418)  /* doorbell strd for pf and vf */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_VF_SIZE_REG                     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA41C)  /* vf size in cpu memory */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQE_RD_MAX_REG                  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA420)  /* the max number of SQE read  back in one sq descrbiton */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_RAM_INITIAL_REG                 (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA424)  /* the max number of SQE read  back in one sq descrbiton */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_INT_TIME_THR_REG                (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA428)  /* time threshlod for int req */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_DDR_STRD_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA42C)  /* ddr stride */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_INT_REQ_REG                     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA430)  /* time threshlod for int req */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_PENDING_0_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA434)  /* nvme interrupt vector pending status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_PENDING_1_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA438)  /* nvme interrupt vector pending status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_PENDING_2_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA43C)  /* nvme interrupt vector pending status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_PENDING_3_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA440)  /* nvme interrupt vector pending status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_PENDING_4_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA444)  /* nvme interrupt vector pending status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_PENDING_5_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA448)  /* nvme interrupt vector pending status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_PENDING_6_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA44C)  /* nvme interrupt vector pending status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_PENDING_7_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA450)  /* nvme interrupt vector pending status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_PENDING_8_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA454)  /* nvme interrupt vector pending status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_PENDING_9_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA458)  /* nvme interrupt vector pending status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_PENDING_10_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA45C)  /* nvme interrupt vector pending status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_PENDING_11_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA460)  /* nvme interrupt vector pending status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_PENDING_12_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA464)  /* nvme interrupt vector pending status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_PENDING_13_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA468)  /* nvme interrupt vector pending status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_PENDING_14_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA46C)  /* nvme interrupt vector pending status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_PENDING_15_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA470)  /* nvme interrupt vector pending status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_MASK_0_REG          (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA474)  /* nvme interrupt vector  mask */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_MASK_1_REG          (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA478)  /* nvme interrupt vector  mask */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_MASK_2_REG          (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA47C)  /* nvme interrupt vector  mask */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_MASK_3_REG          (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA480)  /* nvme interrupt vector  mask */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_MASK_4_REG          (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA484)  /* nvme interrupt vector  mask */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_MASK_5_REG          (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA488)  /* nvme interrupt vector  mask */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_MASK_6_REG          (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA48C)  /* nvme interrupt vector  mask */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_MASK_7_REG          (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA490)  /* nvme interrupt vector  mask */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_MASK_8_REG          (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA494)  /* nvme interrupt vector  mask */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_MASK_9_REG          (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA498)  /* nvme interrupt vector  mask */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_MASK_10_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA49C)  /* nvme interrupt vector  mask */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_MASK_11_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA4A0)  /* nvme interrupt vector  mask */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_MASK_12_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA4A4)  /* nvme interrupt vector  mask */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_MASK_13_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA4A8)  /* nvme interrupt vector  mask */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_MASK_14_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA4AC)  /* nvme interrupt vector  mask */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_VECTOR_MASK_15_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA4B0)  /* nvme interrupt vector  mask */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_0_REG                     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA800)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_1_REG                     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA804)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_2_REG                     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA808)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_3_REG                     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA80C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_4_REG                     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA810)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_5_REG                     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA814)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_6_REG                     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA818)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_7_REG                     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA81C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_8_REG                     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA820)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_9_REG                     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA824)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_10_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA828)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_11_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA82C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_12_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA830)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_13_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA834)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_14_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA838)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_15_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA83C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_16_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA840)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_17_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA844)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_18_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA848)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_19_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA84C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_20_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA850)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_21_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA854)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_22_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA858)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_23_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA85C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_24_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA860)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_25_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA864)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_26_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA868)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_27_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA86C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_28_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA870)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_29_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA874)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_30_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA878)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_31_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA87C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_32_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA880)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_33_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA884)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_34_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA888)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_35_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA88C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_36_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA890)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_37_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA894)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_38_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA898)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_39_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA89C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_40_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8A0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_41_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8A4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_42_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8A8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_43_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8AC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_44_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8B0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_45_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8B4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_46_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8B8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_47_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8BC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_48_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8C0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_49_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8C4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_50_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8C8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_51_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8CC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_52_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8D0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_53_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8D4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_54_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8D8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_55_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8DC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_56_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8E0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_57_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8E4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_58_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8E8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_59_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8EC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_60_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8F0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_61_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8F4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_62_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8F8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_63_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA8FC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_64_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA900)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_65_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA904)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_66_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA908)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_67_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA90C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_68_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA910)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_69_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA914)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_70_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA918)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_71_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA91C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_72_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA920)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_73_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA924)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_74_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA928)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_75_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA92C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_76_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA930)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_77_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA934)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_78_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA938)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_79_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA93C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_80_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA940)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_81_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA944)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_82_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA948)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_83_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA94C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_84_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA950)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_85_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA954)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_86_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA958)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_87_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA95C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_88_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA960)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_89_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA964)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_90_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA968)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_91_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA96C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_92_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA970)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_93_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA974)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_94_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA978)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_95_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA97C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_96_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA980)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_97_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA984)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_98_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA988)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_99_REG                    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA98C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_100_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA990)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_101_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA994)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_102_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA998)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_103_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA99C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_104_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9A0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_105_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9A4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_106_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9A8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_107_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9AC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_108_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9B0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_109_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9B4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_110_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9B8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_111_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9BC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_112_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9C0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_113_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9C4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_114_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9C8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_115_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9CC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_116_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9D0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_117_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9D4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_118_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9D8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_119_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9DC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_120_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9E0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_121_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9E4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_122_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9E8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_123_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9EC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_124_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9F0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_125_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9F4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_126_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9F8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_127_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xA9FC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_128_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA00)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_129_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA04)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_130_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA08)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_131_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA0C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_132_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA10)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_133_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA14)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_134_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA18)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_135_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA1C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_136_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA20)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_137_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA24)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_138_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA28)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_139_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA2C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_140_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA30)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_141_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA34)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_142_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA38)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_143_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA3C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_144_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA40)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_145_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA44)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_146_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA48)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_147_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA4C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_148_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA50)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_149_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA54)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_150_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA58)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_151_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA5C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_152_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA60)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_153_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA64)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_154_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA68)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_155_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA6C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_156_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA70)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_157_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA74)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_158_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA78)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_159_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA7C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_160_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA80)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_161_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA84)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_162_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA88)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_163_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA8C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_164_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA90)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_165_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA94)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_166_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA98)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_167_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAA9C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_168_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAAA0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_169_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAAA4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_170_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAAA8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_171_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAAAC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_172_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAAB0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_173_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAAB4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_174_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAAB8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_175_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAABC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_176_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAAC0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_177_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAAC4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_178_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAAC8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_179_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAACC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_180_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAAD0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_181_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAAD4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_182_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAAD8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_183_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAADC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_184_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAAE0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_185_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAAE4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_186_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAAE8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_187_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAAEC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_188_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAAF0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_189_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAAF4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_190_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAAF8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_191_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAAFC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_192_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB00)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_193_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB04)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_194_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB08)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_195_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB0C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_196_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB10)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_197_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB14)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_198_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB18)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_199_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB1C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_200_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB20)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_201_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB24)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_202_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB28)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_203_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB2C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_204_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB30)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_205_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB34)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_206_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB38)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_207_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB3C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_208_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB40)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_209_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB44)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_210_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB48)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_211_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB4C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_212_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB50)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_213_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB54)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_214_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB58)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_215_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB5C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_216_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB60)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_217_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB64)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_218_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB68)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_219_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB6C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_220_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB70)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_221_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB74)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_222_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB78)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_223_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB7C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_224_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB80)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_225_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB84)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_226_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB88)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_227_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB8C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_228_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB90)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_229_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB94)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_230_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB98)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_231_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAB9C)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_232_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABA0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_233_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABA4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_234_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABA8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_235_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABAC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_236_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABB0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_237_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABB4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_238_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABB8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_239_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABBC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_240_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABC0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_241_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABC4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_242_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABC8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_243_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABCC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_244_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABD0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_245_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABD4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_246_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABD8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_247_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABDC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_248_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABE0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_249_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABE4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_250_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABE8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_251_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABEC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_252_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABF0)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_253_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABF4)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_254_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABF8)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQS_255_REG                   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xABFC)  /* depth of IO SQ Ring */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_0_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC00)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_1_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC08)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_2_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC10)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_3_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC18)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_4_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC20)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_5_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC28)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_6_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC30)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_7_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC38)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_8_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC40)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_9_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC48)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_10_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC50)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_11_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC58)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_12_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC60)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_13_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC68)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_14_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC70)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_15_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC78)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_16_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC80)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_17_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC88)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_18_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC90)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_19_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC98)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_20_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACA0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_21_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACA8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_22_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACB0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_23_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACB8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_24_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACC0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_25_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACC8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_26_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACD0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_27_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACD8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_28_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACE0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_29_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACE8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_30_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACF0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_31_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACF8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_32_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD00)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_33_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD08)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_34_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD10)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_35_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD18)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_36_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD20)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_37_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD28)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_38_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD30)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_39_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD38)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_40_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD40)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_41_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD48)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_42_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD50)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_43_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD58)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_44_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD60)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_45_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD68)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_46_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD70)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_47_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD78)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_48_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD80)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_49_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD88)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_50_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD90)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_51_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD98)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_52_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADA0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_53_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADA8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_54_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADB0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_55_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADB8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_56_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADC0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_57_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADC8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_58_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADD0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_59_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADD8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_60_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADE0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_61_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADE8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_62_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADF0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_63_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADF8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_64_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE00)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_65_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE08)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_66_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE10)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_67_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE18)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_68_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE20)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_69_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE28)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_70_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE30)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_71_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE38)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_72_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE40)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_73_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE48)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_74_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE50)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_75_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE58)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_76_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE60)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_77_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE68)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_78_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE70)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_79_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE78)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_80_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE80)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_81_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE88)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_82_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE90)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_83_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE98)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_84_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAEA0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_85_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAEA8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_86_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAEB0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_87_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAEB8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_88_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAEC0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_89_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAEC8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_90_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAED0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_91_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAED8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_92_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAEE0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_93_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAEE8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_94_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAEF0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_95_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAEF8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_96_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF00)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_97_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF08)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_98_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF10)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_99_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF18)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_100_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF20)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_101_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF28)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_102_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF30)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_103_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF38)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_104_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF40)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_105_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF48)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_106_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF50)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_107_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF58)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_108_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF60)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_109_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF68)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_110_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF70)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_111_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF78)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_112_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF80)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_113_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF88)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_114_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF90)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_115_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF98)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_116_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFA0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_117_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFA8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_118_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFB0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_119_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFB8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_120_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFC0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_121_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFC8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_122_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFD0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_123_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFD8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_124_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFE0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_125_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFE8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_126_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFF0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_127_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFF8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_128_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB000)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_129_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB008)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_130_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB010)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_131_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB018)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_132_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB020)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_133_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB028)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_134_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB030)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_135_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB038)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_136_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB040)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_137_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB048)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_138_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB050)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_139_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB058)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_140_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB060)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_141_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB068)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_142_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB070)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_143_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB078)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_144_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB080)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_145_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB088)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_146_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB090)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_147_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB098)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_148_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0A0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_149_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0A8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_150_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0B0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_151_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0B8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_152_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0C0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_153_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0C8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_154_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0D0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_155_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0D8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_156_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0E0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_157_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0E8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_158_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0F0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_159_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0F8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_160_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB100)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_161_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB108)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_162_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB110)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_163_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB118)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_164_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB120)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_165_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB128)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_166_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB130)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_167_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB138)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_168_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB140)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_169_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB148)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_170_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB150)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_171_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB158)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_172_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB160)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_173_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB168)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_174_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB170)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_175_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB178)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_176_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB180)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_177_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB188)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_178_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB190)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_179_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB198)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_180_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1A0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_181_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1A8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_182_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1B0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_183_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1B8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_184_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1C0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_185_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1C8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_186_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1D0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_187_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1D8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_188_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1E0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_189_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1E8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_190_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1F0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_191_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1F8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_192_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB200)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_193_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB208)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_194_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB210)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_195_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB218)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_196_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB220)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_197_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB228)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_198_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB230)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_199_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB238)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_200_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB240)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_201_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB248)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_202_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB250)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_203_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB258)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_204_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB260)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_205_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB268)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_206_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB270)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_207_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB278)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_208_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB280)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_209_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB288)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_210_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB290)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_211_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB298)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_212_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2A0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_213_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2A8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_214_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2B0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_215_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2B8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_216_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2C0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_217_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2C8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_218_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2D0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_219_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2D8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_220_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2E0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_221_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2E8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_222_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2F0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_223_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2F8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_224_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB300)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_225_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB308)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_226_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB310)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_227_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB318)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_228_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB320)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_229_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB328)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_230_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB330)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_231_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB338)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_232_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB340)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_233_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB348)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_234_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB350)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_235_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB358)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_236_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB360)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_237_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB368)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_238_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB370)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_239_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB378)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_240_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB380)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_241_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB388)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_242_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB390)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_243_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB398)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_244_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3A0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_245_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3A8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_246_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3B0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_247_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3B8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_248_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3C0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_249_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3C8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_250_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3D0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_251_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3D8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_252_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3E0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_253_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3E8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_254_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3F0)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_LOW_255_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3F8)  /* low 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_0_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC04)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_1_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC0C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_2_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC14)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_3_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC1C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_4_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC24)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_5_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC2C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_6_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC34)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_7_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC3C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_8_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC44)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_9_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC4C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_10_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC54)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_11_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC5C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_12_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC64)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_13_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC6C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_14_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC74)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_15_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC7C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_16_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC84)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_17_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC8C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_18_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC94)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_19_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAC9C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_20_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACA4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_21_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACAC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_22_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACB4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_23_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACBC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_24_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACC4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_25_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACCC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_26_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACD4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_27_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACDC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_28_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACE4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_29_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACEC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_30_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACF4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_31_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xACFC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_32_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD04)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_33_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD0C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_34_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD14)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_35_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD1C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_36_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD24)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_37_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD2C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_38_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD34)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_39_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD3C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_40_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD44)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_41_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD4C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_42_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD54)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_43_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD5C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_44_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD64)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_45_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD6C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_46_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD74)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_47_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD7C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_48_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD84)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_49_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD8C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_50_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD94)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_51_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAD9C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_52_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADA4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_53_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADAC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_54_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADB4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_55_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADBC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_56_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADC4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_57_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADCC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_58_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADD4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_59_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADDC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_60_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADE4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_61_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADEC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_62_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADF4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_63_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xADFC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_64_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE04)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_65_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE0C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_66_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE14)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_67_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE1C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_68_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE24)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_69_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE2C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_70_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE34)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_71_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE3C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_72_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE44)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_73_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE4C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_74_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE54)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_75_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE5C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_76_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE64)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_77_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE6C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_78_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE74)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_79_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE7C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_80_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE84)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_81_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE8C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_82_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE94)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_83_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAE9C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_84_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAEA4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_85_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAEAC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_86_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAEB4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_87_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAEBC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_88_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAEC4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_89_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAECC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_90_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAED4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_91_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAEDC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_92_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAEE4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_93_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAEEC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_94_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAEF4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_95_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAEFC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_96_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF04)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_97_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF0C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_98_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF14)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_99_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF1C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_100_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF24)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_101_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF2C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_102_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF34)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_103_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF3C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_104_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF44)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_105_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF4C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_106_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF54)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_107_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF5C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_108_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF64)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_109_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF6C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_110_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF74)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_111_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF7C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_112_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF84)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_113_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF8C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_114_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF94)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_115_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAF9C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_116_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFA4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_117_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFAC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_118_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFB4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_119_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFBC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_120_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFC4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_121_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFCC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_122_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFD4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_123_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFDC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_124_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFE4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_125_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFEC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_126_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFF4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_127_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xAFFC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_128_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB004)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_129_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB00C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_130_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB014)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_131_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB01C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_132_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB024)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_133_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB02C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_134_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB034)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_135_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB03C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_136_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB044)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_137_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB04C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_138_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB054)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_139_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB05C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_140_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB064)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_141_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB06C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_142_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB074)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_143_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB07C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_144_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB084)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_145_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB08C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_146_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB094)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_147_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB09C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_148_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0A4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_149_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0AC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_150_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0B4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_151_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0BC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_152_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0C4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_153_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0CC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_154_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0D4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_155_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0DC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_156_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0E4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_157_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0EC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_158_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0F4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_159_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB0FC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_160_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB104)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_161_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB10C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_162_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB114)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_163_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB11C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_164_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB124)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_165_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB12C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_166_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB134)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_167_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB13C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_168_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB144)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_169_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB14C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_170_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB154)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_171_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB15C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_172_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB164)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_173_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB16C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_174_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB174)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_175_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB17C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_176_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB184)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_177_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB18C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_178_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB194)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_179_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB19C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_180_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1A4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_181_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1AC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_182_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1B4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_183_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1BC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_184_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1C4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_185_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1CC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_186_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1D4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_187_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1DC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_188_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1E4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_189_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1EC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_190_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1F4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_191_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB1FC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_192_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB204)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_193_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB20C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_194_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB214)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_195_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB21C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_196_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB224)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_197_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB22C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_198_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB234)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_199_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB23C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_200_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB244)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_201_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB24C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_202_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB254)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_203_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB25C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_204_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB264)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_205_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB26C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_206_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB274)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_207_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB27C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_208_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB284)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_209_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB28C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_210_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB294)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_211_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB29C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_212_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2A4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_213_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2AC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_214_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2B4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_215_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2BC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_216_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2C4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_217_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2CC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_218_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2D4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_219_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2DC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_220_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2E4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_221_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2EC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_222_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2F4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_223_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB2FC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_224_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB304)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_225_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB30C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_226_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB314)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_227_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB31C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_228_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB324)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_229_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB32C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_230_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB334)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_231_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB33C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_232_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB344)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_233_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB34C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_234_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB354)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_235_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB35C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_236_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB364)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_237_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB36C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_238_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB374)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_239_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB37C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_240_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB384)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_241_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB38C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_242_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB394)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_243_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB39C)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_244_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3A4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_245_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3AC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_246_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3B4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_247_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3BC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_248_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3C4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_249_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3CC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_250_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3D4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_251_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3DC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_252_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3E4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_253_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3EC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_254_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3F4)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_IOSQ_BASE_ADDR_HIGH_255_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB3FC)  /* high 32 bit of nvme SQ Ring base address */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_0_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB400)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_1_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB404)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_2_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB408)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_3_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB40C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_4_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB410)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_5_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB414)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_6_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB418)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_7_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB41C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_8_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB420)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_9_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB424)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_10_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB428)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_11_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB42C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_12_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB430)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_13_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB434)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_14_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB438)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_15_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB43C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_16_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB440)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_17_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB444)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_18_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB448)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_19_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB44C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_20_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB450)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_21_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB454)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_22_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB458)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_23_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB45C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_24_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB460)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_25_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB464)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_26_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB468)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_27_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB46C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_28_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB470)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_29_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB474)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_30_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB478)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_31_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB47C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_32_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB480)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_33_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB484)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_34_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB488)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_35_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB48C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_36_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB490)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_37_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB494)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_38_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB498)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_39_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB49C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_40_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4A0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_41_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4A4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_42_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4A8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_43_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4AC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_44_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4B0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_45_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4B4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_46_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4B8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_47_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4BC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_48_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4C0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_49_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4C4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_50_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4C8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_51_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4CC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_52_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4D0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_53_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4D4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_54_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4D8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_55_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4DC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_56_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4E0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_57_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4E4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_58_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4E8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_59_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4EC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_60_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4F0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_61_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4F4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_62_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4F8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_63_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB4FC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_64_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB500)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_65_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB504)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_66_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB508)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_67_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB50C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_68_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB510)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_69_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB514)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_70_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB518)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_71_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB51C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_72_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB520)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_73_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB524)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_74_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB528)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_75_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB52C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_76_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB530)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_77_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB534)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_78_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB538)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_79_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB53C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_80_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB540)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_81_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB544)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_82_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB548)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_83_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB54C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_84_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB550)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_85_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB554)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_86_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB558)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_87_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB55C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_88_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB560)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_89_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB564)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_90_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB568)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_91_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB56C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_92_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB570)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_93_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB574)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_94_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB578)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_95_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB57C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_96_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB580)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_97_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB584)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_98_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB588)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_99_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB58C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_100_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB590)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_101_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB594)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_102_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB598)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_103_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB59C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_104_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5A0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_105_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5A4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_106_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5A8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_107_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5AC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_108_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5B0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_109_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5B4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_110_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5B8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_111_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5BC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_112_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5C0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_113_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5C4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_114_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5C8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_115_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5CC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_116_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5D0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_117_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5D4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_118_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5D8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_119_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5DC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_120_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5E0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_121_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5E4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_122_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5E8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_123_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5EC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_124_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5F0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_125_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5F4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_126_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5F8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_127_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB5FC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_128_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB600)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_129_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB604)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_130_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB608)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_131_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB60C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_132_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB610)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_133_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB614)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_134_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB618)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_135_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB61C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_136_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB620)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_137_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB624)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_138_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB628)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_139_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB62C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_140_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB630)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_141_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB634)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_142_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB638)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_143_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB63C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_144_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB640)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_145_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB644)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_146_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB648)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_147_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB64C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_148_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB650)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_149_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB654)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_150_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB658)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_151_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB65C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_152_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB660)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_153_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB664)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_154_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB668)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_155_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB66C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_156_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB670)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_157_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB674)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_158_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB678)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_159_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB67C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_160_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB680)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_161_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB684)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_162_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB688)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_163_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB68C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_164_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB690)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_165_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB694)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_166_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB698)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_167_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB69C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_168_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6A0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_169_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6A4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_170_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6A8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_171_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6AC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_172_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6B0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_173_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6B4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_174_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6B8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_175_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6BC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_176_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6C0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_177_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6C4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_178_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6C8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_179_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6CC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_180_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6D0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_181_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6D4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_182_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6D8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_183_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6DC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_184_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6E0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_185_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6E4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_186_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6E8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_187_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6EC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_188_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6F0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_189_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6F4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_190_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6F8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_191_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB6FC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_192_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB700)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_193_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB704)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_194_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB708)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_195_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB70C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_196_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB710)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_197_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB714)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_198_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB718)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_199_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB71C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_200_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB720)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_201_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB724)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_202_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB728)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_203_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB72C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_204_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB730)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_205_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB734)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_206_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB738)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_207_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB73C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_208_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB740)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_209_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB744)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_210_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB748)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_211_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB74C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_212_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB750)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_213_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB754)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_214_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB758)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_215_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB75C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_216_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB760)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_217_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB764)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_218_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB768)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_219_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB76C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_220_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB770)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_221_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB774)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_222_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB778)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_223_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB77C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_224_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB780)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_225_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB784)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_226_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB788)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_227_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB78C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_228_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB790)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_229_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB794)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_230_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB798)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_231_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB79C)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_232_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7A0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_233_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7A4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_234_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7A8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_235_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7AC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_236_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7B0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_237_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7B4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_238_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7B8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_239_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7BC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_240_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7C0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_241_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7C4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_242_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7C8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_243_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7CC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_244_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7D0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_245_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7D4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_246_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7D8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_247_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7DC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_248_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7E0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_249_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7E4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_250_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7E8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_251_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7EC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_252_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7F0)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_253_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7F4)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_254_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7F8)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQR_MEMORY_RD_PTR_255_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xB7FC)  /* local CPU memory rd_ptr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQ_SIZE_RAM_ECC_INJECT_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xC000)  /* sq size ram ecc inject */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQ_SIZE_RAM_ECC_ADDR_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xC004)  /* sq size ram ecc addr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQ_BAL_RAM_ECC_INJECT_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xC008)  /* sq base address low ram ecc inject */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQ_BAL_RAM_ECC_ADDR_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xC00C)  /* sq base address low ram ecc addr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQ_BAH_RAM_ECC_INJECT_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xC0010) /* sq base addr high ram ecc inject */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQ_BAH_RAM_ECC_ADDR_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xC0014) /* sq base addr high ram ecc addr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_RD_PTR_RAM_ECC_INJECT_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xC0018) /* read pointer ram ecc inject */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_RD_PTR_RAM_ECC_ADDR_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xC001C) /* read pointer ram ecc addr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQ_DES_RAM_ECC_INJECT_REG       (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xC020)  /* sq description ram ecc inject */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SQ_DES_RAM_ECC_ADDR_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xC024)  /* sq description ram ecc addr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PRFETCH_FIFO_RAM_ECC_INJECT_REG (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xC028)  /* prefrtch fifo ram ecc inject */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PRFETCH_FIFO_RAM_ECC_ADDR_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xC02C)  /* prefrtch fifo ram ecc addr */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_LINK_DOWN_PROC_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xCC00)  /* nvme link down processs */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_FLR_STS_REG                (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xCD00)  /* nvme FLR request */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_DMACQ_ERR_STS_REG          (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xCE00)  /* nvme DMACQ err stst */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_SQ_DES_RAM_CFG_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xCF00)  /* nvme_sq_des_ctrl_ram_dfx_cfg */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_SQ_DES_RAM_WDAT_L_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xCF04)  /* nvme_sq_des_ctrl_ram_wr_data_low */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_SQ_DES_RAM_WDAT_H_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xCF08)  /* nvme_sq_des_ctrl_ram_wr_data_high */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_SQ_DES_RAM_RDAT_L_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xCF0C)  /* nvme_sq_des_ctrl_ram_rd_data_low */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_SQ_DES_RAM_RDAT_H_REG      (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xCF10)  /* nvme_sq_des_ctrl_ram_rd_data_high */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_FIFO_STS_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xCF14)  /* nvme_fifo_sts */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_FSM_STS_REG                (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xCF18)  /* nvme_fsm_status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_FLOW_STS0_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xCF1C)  /* nvme_flow_sts */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_FLOW_STS1_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xCF20)  /* nvme_flow_sts */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_QUEUE_STS0_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xCF24)  /* nvme_queue_stst0 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_QUEUE_STS1_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xCF28)  /* nvme_queue_stst1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_QUEUE_STS2_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xCF2C)  /* nvme_queue_stst2 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_QUEUE_STS3_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xCF30)  /* nvme_queue_stst3 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_QUEUE_STS4_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xCF34)  /* nvme_queue_stst4 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_QUEUE_STS5_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xCF38)  /* nvme_queue_stst5 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_QUEUE_STS6_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xCF3C)  /* nvme_queue_stst6 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_QUEUE_STS7_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xCF40)  /* nvme_queue_stst7 */

#endif // __HIPCIEC_NVME_GLOBAL_REG_REG_OFFSET_H__
